1. Field of the Invention
The present invention relates to a semiconductor memory such as a static memory, in particular, to a technology for optimally setting driving timing of a sense amplifier.
2. Description of the Related Art
Generally, in a semiconductor memory such as a static memory, a memory cell is selected with a word line signal. Data are read from a selected memory cell to a bit line. A read voltage on the bit line is amplified by a sense amplifier. As a result, data stored in the memory cell are read. Timing at which the sense amplifier starts amplifying the read voltage is set with a sense amplifier start signal. It is preferred that when the read voltage on the bit line can be amplified by the sense amplifier, the sense amplifier start signal is activated. When the timing at which the sense amplifier start signal is activated comes earlier, data cannot be correctly read. In contrast, when the timing at which the sense amplifier start signal is activated delays, the access time is elongated.
To activate the sense amplifier start signal at the optimum timing, a static memory that has a plurality of dummy memory cells that are used to adjust timing (referred to as timing adjustment dummy memory cells) and a plurality of dummy memory cells used to load bit lines (referred to as load dummy memory cells) has been proposed (for example, Japanese Unexamined Patent Application Publication No. 2003- 366781). In the static memory, the timing adjustment dummy memory cells are connected to a dummy word line. The gates of transfer transistors of the load dummy memory cells are connected to a ground line. Each of the timing adjustment dummy memory cells and each of the load dummy memory cells store reverse logics and are connected to common complementary bit lines. When each timing adjustment dummy memory cell is driven with the dummy word line, the voltage on each bit line varies without influence of a leakage current that flows from each load dummy memory cell to each bit line. Thus, the sense amplifier start signal is activated at desired timing in accordance with the number of timing adjustment dummy memory cells. On the other hand, when the threshold value of a transistor is low due to fluctuation in a fabricating condition of a semiconductor memory, the drivability of the timing adjustment dummy memory cells improves. Thus, the activation timing of the sense amplifier start signal comes earlier. In contrast, when the threshold voltage of a transistor is high, the activation timing of the sense amplifier start signal delays.